1. Field of the Invention
The present invention relates to techniques for communicating signals in multi-chip systems. More specifically, the present invention relates to a multi-chip system which includes semiconductor dies that communicate signals using on-chip photonics.
2. Related Art
Many computer systems and networks include modules, such as switches, to selectively communicate data items between different system components. These switches often include multiple input ports and multiple output ports, which are often implemented as high-speed serial input/output (I/O) ports. In contrast with lower-speed parallel ports, these high-speed serial ports offer advantages, such as reducing overall power consumption and reducing associated port area (in terms of the number of printed circuit boards, chip packages, and/or I/O connectors). However, high-speed serial ports typically require additional circuits, including: circuits to serialize and deserialize data; circuits to encode and decode data; and circuits to recover an embedded clock. These additional circuits typically consume a significant amount of the area on an integrated circuit. Consequently, these additional circuits may partly determine the size and complexity of a chip.
Furthermore, many existing switches are based on a memory switch architecture. In this type of architecture, a switch includes a shared multiple-port memory that includes one or more logical buffers that selectively couple input ports to output ports based on a switch configuration (which may be based on header information in data packets). This memory-switch architecture provides sufficient memory bandwidth to ensure that the input ports can simultaneously write data into the buffer memories, thereby avoiding data collisions. Note that buffer memory is typically high-bandwidth memory that is often implemented on-chip. Therefore, the amount of buffer memory may also determine the size of a switch.
If the scale of the switch does not allow for a single-chip implementation, the switch may be partitioned among several chips with each chip providing a fraction of the aggregate switching capacity. Such multiple-chip implementations are often based on architectures that include multiple switching stages or multiple switching planes.
Unfortunately, it is often challenging to provide interconnects in a multi-chip switch with an aggregate bandwidth that is sufficient to accommodate the total bandwidth of the signals received by the switch. Consequently, interconnects in large-scale switches may be complicated and expensive. For example, existing switches that offer multiple Tb/s capability typically include multiple racks with cabling between the racks to provide interconnects that can accommodate the full bandwidth of the switch.
Therefore, multi-chip switches often have large footprints and consume significant amounts of power. Moreover, as the size of a given switch increases, it may be more difficult to control due to increased delays and latency. This, in turn, may lead to problems associated with coordinating or scheduling the data flow in the switch. The complexity and expense associated with the components used to address these problems can greatly impact the performance and reliability of multi-chip switches.
For example, flow-control techniques have been used to address the problems of delays and latency in switches. In particular, flow-control information (such as routing packets) has been used to configure switching paths in an all-electrical or an all-optical switch fabric. Note that in an all-electrical (or all-optical) switch fabric signals typically remain in the electrical (or the optical) domain and the switching is performed by all-electrical (or all-optical) devices based on electrical (or optical) flow-control information.
This configuration technique enables bandwidth and buffers to be reserved so the data experiences a reduced delay and latency as it traverses the switch. Unfortunately, it is difficult to effectively send routing packets ahead of data packets in a switch. Consequently, existing techniques have either intentionally slowed down the switch or have temporarily stored data in buffer memories. In either case, the potential improvement in data latency offered by using flow-control information is reduced and extra resources (such as power consumption and integrated-circuit area) are required.
Hence, what is needed is a method and an apparatus that facilitates switching without the problems listed above.